Boundary Scan Testing (JTAG IEEE 1149.1)

In acknowledgment of superior technical capability and advanced application expertise in Boundary-Scan Testing and In-System Programming, ACD has been recognized as an Authorized Applications Partner of JTAG Technologies Inc.

With the addition of JTAG Technologies, Inc. Boundary Scan Test tools, ACD is now offering our customers full JTAG consultation and test coverage for designs that employ Boundary Scan components.

In addition to Boundary Scan Testing, ACD also offers In-System programming of Programmable Logic Devices such as FPGA’s and Flash memories.

Benefits of Boundary Scan Design

As pin counts increase device sizes decreases thus providing for more and more complex and dense designs.

Today’s designs, which employ large pin count Ball-Grid-Array and micro-BGA components, create seemingly un-surmountable challenges to produce a printed circuit board with adequate test points. If the designer is successful, then the test engineer is faced with the challenge of creating a bed-of-nails fixture that will adequately probe the thousand of possible test points. Given that this is possible, then management is faced with the reality that the cost of such test fixtures will easily exceed tens of thousands of dollars. Thus the cost of test may have serious impact on the profit margin.

Faced with such design, test and management challenges, a promising design can quickly find it’s way into the “wait for a better time” basket.

Fortunately there is a technology that overcomes these problems: “Boundary Scan Components (JTAG IEEE 1149.1)”

Designs can employ the greatest densities without worrying about test coverage, test engineering no longer has to worry about creating multi-thousand probe bed-of-nails test fixtures and management no longer has to worry about budgeting for the cost of such expensive test fixtures. The solution is to employ “Boundary Scan Testing” in the design.

ACD Boundary Scan Consultation/Testing Services

ACD is pleased to announce the addition of JTAG Technologies test tools with which we can provide our customers with full JTAG testing and In-System programming.

ACD now provides:

v     Design consultation during the design and layout phase of any design aiding the customer in the efficient use of the Boundary Scan chain(s). This includes an analysis of the test coverage provided by the inclusion of Boundary Scan components.

v     Boundary Scan Test programming that includes the testing of the Boundary Scan chain infrastructure, the Boundary Scan Interconnect, accessible logic clusters and memories.

v     In-System Programming of programmable logic devices.

v     Complete Boundary Scan testing after assembly. Thus providing the customer with highly reliable product that can be quickly verified and integrated into their products for sale.

Typical Test Program Input Criteria

To begin the consultation/test programming process ACD requires the following items from the customer:

v     Latest Design Schematic

v     Latest Design Net List

v     Accurate and Complete Bill-Of-Materials

v     Boundary Scan Device Logic files (BSDL) for all Boundary Scan components in the design.